Metal oxide semiconductor field effect transistors (MOSFETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Conventional planar MOS transistors include a gate structure or stack formed on a semiconductor substrate. The gate stack generally includes a thin gate dielectric overlying the substrate and a gate electrode situated over the gate dielectric. Source and drain regions are formed in the substrate on either side of the gate structure, thereby defining a channel region at the upper surface of the substrate under the gate structure.
In operation, the gate electrode is energized to create an electric field in the channel region of the substrate, thus inverting a thin portion of the channel underneath the gate dielectric and allowing minority carriers to travel through the channel between the source/drain regions. The threshold voltage (Vt) of a transistor is the gate voltage value required to render the channel conductive by formation of an inversion layer (e.g., in which the concentration of minority carriers exceeds that of majority carriers) at the surface of the semiconductor substrate under the gate stack.
Scaling is a continuing process in the manufacture and design of semiconductor products, wherein electrical device feature sizes are being reduced to increase device density, improve performance (e.g., increase switching speed), and to reduce power consumption, for example. It is desirable, for instance, to scale or reduce the length of the transistor gate stack and hence the length of the channel between the source and drain regions, to increase drive current performance, particularly for operation with reduced gate voltages. The length of the gate structure is typically the smallest dimension in a planar transistor. However, lithography generally limits the extent to which transistor dimensions can be reliably scaled, wherein the minimum gate length is typically limited to the smallest dimension that can be repeatably patterned and etched using current photolithographic and etching techniques.
In addition to fabrication process limitations, performance limitations are also a barrier to scaling conventional planar transistor dimensions, particularly the gate length. For example, as the gate length is reduced, the transistor performance may be degraded by short channel effects. In devices having longer channels, the gate voltage and the resulting field primarily control the depletion of charge under the gate. In shorter channel devices, however, the channel region is also affected by the source and drain voltages, leading to increased off state current due to Vt roll off, degraded subthreshold slope, and degraded output current. In addition, since less gate voltage is needed to deplete the shortened channel, the barrier for electron injection from the source to the drain decreases, a situation sometimes referred to as drain induced barrier lowering (DIBL).
As the performance and process limitations on scaling planar transistors are reached, attention has been recently directed to transistor designs having “multiple gates” (e.g., non planar MOS transistors). In theory, these designs provide more control over a scaled channel by situating the gate electrode, around two or more sides of the channel, whereby a shorter channel length can be achieved for the same gate dielectric thickness or similar channel lengths can be used with thicker gate dielectrics. This generally provides for improved current drive and short channel characteristics due to the additional control afforded by the increased amount of gate electrode material.
FIGS. 1 and 2 illustrate examples of some multiple gate transistor designs, which are generally named after the shape of their respective gate structures. Dual and triple gate transistors 102 and 104 are respectively illustrated in FIG. 1, while a quad gate transistor 106, and a “PI” gate transistor 108 are presented in FIG. 2. The transistors are formed in a silicon over insulator (SOI) wafer 110, which includes a silicon substrate 112 with an overlying oxide insulator 114 and a 20.0-50.0 nm thick semiconductor layer (not shown) above the oxide 114. In forming the transistors, the upper semiconductor layer is etched away, leaving isolated islands or blocks 116 of semiconductor material, and a gate structure (G) is formed over the silicon blocks 65, with the ends of the blocks 116 being doped to form source (S) and drain (D) regions therein, as illustrated in FIGS. 1 and 2. Multi gate designs offer the prospect of improved transistor performance by alleviating short channel effects seen in scaled planar transistors. This is due primarily to the ability to control the electric field the channel silicon because the gate extends on more than one peripheral side of the channel.
In addition to inversion mode multi gate transistors, accumulation mode multi gate devices are also being explored as yet a further extension of alternative transistor designs. Accumulation mode transistor devices generally offer high current drive and reduced short channel effects, where the threshold voltage in such devices is limited by the amount of doping atoms that can be placed in the small channel region volume and by the choice of available gate materials. As such, the use of accumulation mode structures increases the range of available threshold voltages and offers additional performance in deep submicron structures, especially as the use of Schottky source and drain devices is contemplated.
In operation, when an accumulation mode transistor is turned on an accumulation layer is formed at he top, left and right interfaces of the device. At the same time, the body (or the “volume”) of the device is quasi neutral (i.e., not depleted). The total current in the device is the sum of the current in the accumulation channels and in the neutral body. When the device is turned off, the depletion regions arising from the interfaces meet near the center of the device and pinch off the quasi neutral piece of silicon connecting the source and drain regions. This pinch off mechanism works well as long as the amount of dopant atoms remains relatively low. An increased dopant concentration, however, can result in a sufficient number of electrons (or electron concentration) being present in the channel region so that a leakage current develops in the channel region. This is particularly, true as scaling progresses and channel lengths are resultantly decreased. It will be appreciated that while the case of an n-channel device is discussed herein, the general principles described also apply to p-channel devices, provided that the appropriate polarity changes are applied to the dopant atoms and applied biases.
This is illustrated in FIGS. 3-10 wherein different channel lengths and dopant concentrations are illustrated that may (or may not) culminate in leakage currents. In FIGS. 3 and 4, for example, a first PI gate accumulation mode multi gate transistor device 300 is illustrated, where FIG. 4 is a cross sectional view of FIG. 3 taken along lines 4-4. The transistor device 300 has a gate structure 302 that overlies a channel region 304. Gate electrode material 306 of the gate structure 302 extends into a buried oxide 308 of the transistor 300, and source (S) and drain (D) regions 310, 312 of the transistor 300 are located on either side of the channel region 304. The gate electrode material 306 is not shown in FIG. 4. In this example, the channel 304 has a length of L=80 nm and a doping concentration of 1017 cm−3. In this situation, a conduction path 314 does not fully connect or does not form in the channel region 304. As such, the relatively long channel length and the relatively low dopant concentration results in little to no electrons in the channel region, and the likelihood of a leakage current developing therein is therefore virtually nonexistent when the device is off (VG=0V and VD=1V).
In FIGS. 5 and 6, a second PI gate accumulation mode multi gate transistor device 500 is illustrated, where FIG. 6 is a cross sectional view of FIG. 5 taken along lines 6-6. The transistor device 500 once again has a gate structure 502 that overlies a channel region 504, with gate electrode material 506 of the gate structure 502 extending into a buried oxide 508 of the transistor 500, and source (S) and drain (D) regions 510, 512 of the transistor 500 being located on either side of the channel region 504. The gate electrode material 506 is not shown in FIG. 6. In this example, the channel region 504 again has a length of L=80 nm, but the doping concentration is increased to 1018 cm−3. In this situation, a conduction path 514 may begin to develop within the channel region 504. Even with the increased dopant concentration, however, the relatively long channel length still provides enough separation between the source region 510 and the drain regions 512 so that the number of electrons in the channel region 504, if any, remains relatively insufficient to cause a leakage current to develop in the channel region 504 when the device 500 is off (VG=0V and VD=1V).
FIGS. 7 and 8 illustrate a third PI gate accumulation mode multi gate transistor device 700, where FIG. 8 is a cross sectional view of FIG. 7 taken along lines 8-8. A gate structure 702 of the transistor device 700 overlies a channel region 704, with gate electrode material 706 of the gate structure 702 extending into a buried oxide 708 of the transistor 700. Source (S) and drain (D) regions 710, 712 of the transistor 700 are located on either side of the channel region 704. The gate electrode material 706 is not shown in FIG. 8. In this example, the length of the channel region 704 is reduced to L=30 nm, with the doping concentration at 1017 cm−3. In this situation, a more pronounced conduction path 714 is developed in the channel region 704 and the reduced channel length allows a concentration of 1016 cm−3 electrons to build up in the channel region 704. Nevertheless, this electron accumulation still may be insufficient for a leakage current to develop in the channel region 704 when the device 700 is off (VG=0V and VD=1V).
FIGS. 9 and 10 illustrate a fourth and final example of a PI gate type accumulation mode multi gate transistor device 900, where FIG. 10 is a cross sectional view of FIG. 9 taken along lines 10-10. A gate structure 902 of the transistor device 900 overlies a channel region 904 of the device 900. Gate electrode material 906 of the gate structure 902 extends into a buried oxide 908 of the transistor 900, and source (S) and drain (D) regions 910, 912 of the transistor 900 are located on either side of the channel region 904. The gate electrode material 906 is not shown in FIG. 10. In this example, the length of the channel region 904 is again reduced to L=30 nm, with the doping concentration elevated back up to 1018 cm−3. In this situation, a substantial conduction path 914 is established in the channel region whereby a virtually equivalent number of electrons are able to accumulate in the channel region 904 giving rise to an unwanted leakage current in this region when the device 900 is off (VG=0V and VD=1 V).
Accordingly, there remains a need for improved transistor devices and manufacturing techniques to realize the advantages of scaling while mitigating or avoiding short channel effects, such as the formation of leakage paths, for example, particularly where an increased doping concentration is implemented in accumulation mode multi gate transistor devices.